How to speed up Fmax
How to speed up Fmax
(OP)
Hi,
I put a timing requirement on my clk signal and after I run through synthesis (VHDL code), I get a warning saying that Fmax could not be met. The part is pretty full (98%) and I can't change the part at this point in time. Any suggestions on how I can speed up Fmax??
Thanks,
swb1
I put a timing requirement on my clk signal and after I run through synthesis (VHDL code), I get a warning saying that Fmax could not be met. The part is pretty full (98%) and I can't change the part at this point in time. Any suggestions on how I can speed up Fmax??
Thanks,
swb1





RE: How to speed up Fmax
TTFN
RE: How to speed up Fmax
Thanks,
swb1
RE: How to speed up Fmax
These are not problems to ask random strangers, since they require detailed analysis of your design and application. You should be consulting the other engineers at your company.
TTFN
RE: How to speed up Fmax
RE: How to speed up Fmax
Look for statements that cause multiple loops through the same logic device as this can add a tremendous amount of delay to the processing. Use the reports from the synthesis tool for help in determining where to start.
Unless you can find a way to trim the amount of logic down, I think you really should look at a larger device. While it is a personal opinion, I think if you area already at 98% capacity and working on the new design that you are asking for trouble, at least in production if not in development.