JTAG bit banging
JTAG bit banging
(OP)
I need to bit bang a JTAG interface and I'm not sure how to do it. The JTAG signals are connected to I/Os on a FPGA. I have downloaded the JTAG spec and am having troubles wading through it.
The chip I'm programming is a clock generator. Not the same one I asked questions about earlier this week. The clock generator manufacturer gave me a software tool to create a profile. They also gave me some software that will convert this to JEDEC, SVF or VME files. I will be able to download the JEDEC file to the chip through a JTAG cable.
On top of downloading through the JTAG cable we want the ability to program the chip by bit banging the JTAG signals. I've done I2C, SPI and DBUS but this seems a little more involved. But I'm probably not seeing the trees through the forrest.
thanks for any help
The chip I'm programming is a clock generator. Not the same one I asked questions about earlier this week. The clock generator manufacturer gave me a software tool to create a profile. They also gave me some software that will convert this to JEDEC, SVF or VME files. I will be able to download the JEDEC file to the chip through a JTAG cable.
On top of downloading through the JTAG cable we want the ability to program the chip by bit banging the JTAG signals. I've done I2C, SPI and DBUS but this seems a little more involved. But I'm probably not seeing the trees through the forrest.
thanks for any help





RE: JTAG bit banging
Why are you bit banging?
Why don't you use a cheap programmer like everyone else?
Or are you embedding the FPGA and going to load it each time on boot?
RE: JTAG bit banging
I started reading the spec and some other literature and I think I can do it. But I was just wondering if anyone had any crib notes on it.
thanks
RE: JTAG bit banging
Starting point:
http://www.google.com/search?q=jtag+parallel
You might wind up at some rather dubious hacker websites, so ensure that your virus protection is up-to-date before you go too deep.
RE: JTAG bit banging
By bit-banging the JTAG signals through embedded software I can load a new profile in the clock synthesizer (sp?) on the fly. Of course by doing this you use lock but my application can be halted.
RE: JTAG bit banging
As it turns out I am going to have to do a very similar task. I communicate with my system via a bi-directional parallel port. Now some bright spark has put on a requirement to download the FPGA code at run time! So I have stuck a CPLD on the parallel port wired up to the JTAG programming pins on the Altera FPGA. Now all(!) I have to figure out is what pattern to bang on the parallel port and what code to write into the CPLD.
What is the JTAG spec you downloaded and more specifically where did you download it from?
RE: JTAG bit banging
ht
Dan
Owner
http://www.Hi-TecDesigns.com
RE: JTAG bit banging
The bright spark comment is pretty funny. I'll send residuals to you every time I use it.
macgyver,
I guess the name says it all. That is a great link and I intend on reading it right away. BTW, great web-site and products Dan. Looks like a lot of fun. Are you still doing those products?
RE: JTAG bit banging
This link may or may not be of interest to you.
http://warmcat.com/milksop/cheaptag.html
Salient points are:
# Suitable for 5V-tolerant designs only (eg, 9500, 9500XL)
# The Xilinx software accepts it as a Xilinx Parallel cable without any configuration being necessary
I have not used it. I just tucked it away for reference.
Hence, caveat emptor!
Cheers,
Rich S.
RE: JTAG bit banging
Yep, still working on it, but design has slowed down considerably since I took an 8-5 thing again... real work always seems to get in the way of me playing :) Still designing, having a lot of fun at it, but I'll be announcing an entirely new lineup of products once I have them ALL finished... for the moment the current list is acceptable to me. The hardest part? Making something that's ultra-cool and not being able to tell/show anyone :(
Oh, and on the app note... I didn't notice it myself the first time through and it confused the you-know-what out of me... there are TWO state machines being kept track of, one as part of the PC side of the programmer, and the other as what's going on inside the chip itself (the hardware-based state machine). Once you keep those two straight it's a lot easier to grasp.
Dan
Owner
http://www.Hi-TecDesigns.com
RE: JTAG bit banging
I realized that this is a pretty old post, but I happened to find this thread because I am trying to do almost exactly the same thing as mm. I want to do ISP to an Altera PLD using JTAG with a SVF file. I kind of pieced together what the SVF is describing, but I am having trouble finding the following:
1. When a command is issued (in SVF), what should the waveform look like? Is there a table somewhere that I can see how to big-bang each command?
2. How do I change states in TAP controller?
3. Or rather, where can I find the JTAG spec? mm, do you happened to still have that spec handy? :)
Any help would be greatly appreciated.
Thanks,
Jack
RE: JTAG bit banging
Another engineer actually took up this cause. It is pretty interesting. The other engineer actually has something finished but I haven't been able to try it out. Stay in touch and I'll let you know what I find.
gf
RE: JTAG bit banging
Dan
Owner
http://www.Hi-TecDesigns.com
RE: JTAG bit banging
Keith Cress
Flamin Systems, Inc.- <http://www.flaminsystems.com>
RE: JTAG bit banging
RE: JTAG bit banging
Slightly off topic, but you started it! My last client gave me a big brand spanking new Agilent analyzer to use for their work. It runs the windows OS and connects to the net. First time that I've ever had a logic analyzer that I had to worry about viruses.....
In any event. For my own use, I went with a little more "cost effective" solution. I haven't used it much yet, but what I have done with it seems to be fine. At about $400.00 vs. the multi K$ Agilent one, well........
USB, pretty darn fast. Small. I can take it with me in the laptop case no problem. Triggering isn't too sophisticated, but most of the time it will work. You might have to slow down some of the FPGA designs for it, but for standard embedded micros, this works fine.
Here's the link. I am in no way associated with these guys. They just seem to have a reasonable product.
http://www.pctestinstruments.com/
Hope that this helps. Boy, this IS an old thread. I'd forgotten about it.
Cheers,
Rich S.
RE: JTAG bit banging
If you are talking logic analyzers(not protocol) then I can vouch for this one:
http://www.tech-tools.com/dv_main.htm
Works VERY well. Pretty small. Like all analyzers it takes forever to hook up all the little bitty grabbers but then hands you the answer in a second.. Kinda anticlimactic.
Keith Cress
Flamin Systems, Inc.- <http://www.flaminsystems.com>