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Problem of simulation

Problem of simulation

Problem of simulation

(OP)
Good morning,

I am using protel for a project and I have a problem to simulate my circuit. I use a Wien bridge to generate a sinosidale oscillation. Then this signal pass through a buffer (AOP follower) and then it enters an output stage (class A, common collector).

The simulation works when I do not put a linker capacitor between the buffer and the output stage. I need the capacitor to biase the base of my transistor (the transistor of the ouput stage) to 6.7V. When I put it, I have got an error message :
"doAnalyses: Timestep too small
run simulation(s) aborted"
Could you help me ?

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