DSP Related Question
DSP Related Question
(OP)
All,
I have recently begun prototyping a new DSP based circuit using a TI 320F2812. I have noticed something unexpected and I was wondering if anybody, who has used TI DSPs before, has ever encountered this.
The problem is that occassionally. while running an application out of flash that the external interface output clock (XCLKOUT) takes on an odd value. Specifically, the clock into the DSP is a 30MHz clock, which has been verified as generating 30Mhz. The device is configured to use the internal PLL to convert this to a 120MHz clock. The output clock takes the CPU clock and divides this by 4. Therefore, I should expect a 30MHz clock output, which is what I get most of the time. Ocassionally, after a reset, I am getting a 3.75Mhz (square wave) output instead. If I disable the PLL I always get the 7.5MHz clock out that I would expect as the input clock is 30MHz.
Again, my question is..has anybody experienced this before?
I have noticed that when this happens that the clock output appears as a square wave on the scope. I am not certain if this is part of the issue, or that my limited probe and scope bandwith cause the higher clock frequencies to appear more sinusoidal due to filtering affects.
Also, as I mentioed above, this problem so far has only appeared when operating out of the flash memory as opposed to emulator ram.
I have recently begun prototyping a new DSP based circuit using a TI 320F2812. I have noticed something unexpected and I was wondering if anybody, who has used TI DSPs before, has ever encountered this.
The problem is that occassionally. while running an application out of flash that the external interface output clock (XCLKOUT) takes on an odd value. Specifically, the clock into the DSP is a 30MHz clock, which has been verified as generating 30Mhz. The device is configured to use the internal PLL to convert this to a 120MHz clock. The output clock takes the CPU clock and divides this by 4. Therefore, I should expect a 30MHz clock output, which is what I get most of the time. Ocassionally, after a reset, I am getting a 3.75Mhz (square wave) output instead. If I disable the PLL I always get the 7.5MHz clock out that I would expect as the input clock is 30MHz.
Again, my question is..has anybody experienced this before?
I have noticed that when this happens that the clock output appears as a square wave on the scope. I am not certain if this is part of the issue, or that my limited probe and scope bandwith cause the higher clock frequencies to appear more sinusoidal due to filtering affects.
Also, as I mentioed above, this problem so far has only appeared when operating out of the flash memory as opposed to emulator ram.





RE: DSP Related Question
RE: DSP Related Question
I had searched through their knowledegbase and didn't see anything pertinant, though I didn't think about their discussion forums.
RE: DSP Related Question
it looks like PLL does not lock or disabled.
Please try to check XPLLDIS signal upon reset(datsheet says PLL will be completly disabled) if it is
low then core will run at crystal frequency.
RE: DSP Related Question
http://www.dsp-bg.info/
RE: DSP Related Question
I have noticed that if I power the board up, but do not start the processor (by running the emulator) that the clock output appears to be running at 3.75Mhz.
At the moment, I am thinking that the oscillator issue may have something to do with the reset circuit, as in I may not have implemented it properly. I copied some portions of the circuit that I didn't fully understand from the reference design. In the reference, the reset circuit from the power monitoring ICs is routed through a PLD/FPGA so that it can be ANDed with the reset from the J-TAG emulator.
I am thinking that the reset pulse may be shorter than the time required for the FPGA to get configured from the serial prom - or something along those lines...
I have left this issue on hold for the moment as I am working on proving out the reset of the hardware, which so far is going well.
By the way, I wanted to mention that I took a brief look at the link you posted. It appears, at first glance, that it may be a valuable info resource. I noticed that there are discussion groups on the implementation of hardware and software, which caught my attention. Personally, I am finding that there appears to be a gap between the mathematical side of DSP and the efficient implementation of the algorithms and I was hoping to find some resources to help bridge that gap.
RE: DSP Related Question
Dan
Owner
http://www.Hi-TecDesigns.com
RE: DSP Related Question
One of the biggest savings in DSP code is getting the most svelt algorithm. I find that Crenshaw in the magazine "Embedded Systems Programming - Embedded.com" is a wizard in this stuff. He designs flight controllers which need to robust and efficient. Check his articles out when you get an opportunity. If you have a *very* specific question about an algorithm you can always email him.
http://www.embedded.com/columns/pt
RE: DSP Related Question
At this time, I don't have a specific question, though I am certain that I will in the near future.
Like I mentioned earlier, I have been studying DSP for about four years now and I feel as though I am just starting to intuitively understand some of the fudamental concepts. I am refering to subjects such as the relationship between the response of a continuous time LTI system (defined in a differential equation in S) and a discrete time difference implementation in Z. I have spent a lot of time playing around with tools such as Mathcad and Octave (matlab) calculating out continuous time filter equations, performing transforms on them and plotting frequency responses of equations, etc. I have recently learned that there are multiple forms / ways to implement the equations, as opposed to the direct form simulations and that these forms have an effect on issues such as register overflow.
I am planning on taking advantage of the fact that I have designed a DSP into the project I am working on which will ultimately require power quality analysis and sensor monitoring. Hopefully in a couple of months, I will have the prototype hardware fully functional and have low level drivers written so that I can begin investigating and implementing of some of the math processing.
When I was in undergrad school, there were little to no classes available on these subjects. Consequently, my study has all been self taught. I am seriously considering returning to graduate school (I stopped going to school when I moved a couple of years ago) and one of my key areas of interest is in DSP, which is now an available subject.
RE: DSP Related Question
RE: DSP Related Question
I'm not saying the courses are worthless, only be prepared to receive a lot of theory that needs a lot of tinkering to make sense in the real world... in other words, you'll still have a large learning curve after the class to apply it in a real-world situation.
Once you get past the various algorithmic morphing stages (and a true understanding of the algorithm goes a long way to making a proper implementation), you'll bump into architecture-specific issues (like cache sizes, multiple linked caches, etc.). If you've already started playing with DSPs and their code, you may get a more significant benefit from a computer architecture course, rather than a DSP-specific course. I never had something like that, unfortunately, so I have spent a great deal of time over the years learning basic architectures and how they interoperate... VERY useful stuff when you need to squeeze out those last few clock cycles.
Dan
Owner
http://www.Hi-TecDesigns.com
RE: DSP Related Question
I received my undergrad degree from Univ of Akron and started my graduate work at Case Western Reserve. Having experienced the different schools, I can certainly appreciate the value of a good school. As a result, when I do decide to return to school it will be at the best one I can find. For me at the moment, that would probably be NC-State, which is about 80 miles from me one way. That is probably the biggest impediment to my returning.