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16V8 and other SPLD - power consumption

16V8 and other SPLD - power consumption

16V8 and other SPLD - power consumption

(OP)
Hi,

I will probably need to replace a bunch of CMOS (74HCTxx) with Lattice (or Altera) PLDs. But it seems to be a problem with current consumption. I can have devices that guzzle up to 100 mA and it does not look like the current goes down much when the clock is taken down.

And what about the Altera "turbo" thing? Is it needed to keep speed up? And what will the power consumption be if turbo is turned off - and what will the delay be like?

I really need some input here. What makes are there? What selection criteria are there? Pitfalls?

RE: 16V8 and other SPLD - power consumption

I think you'll just need to look around.  

Cypress has some devices that appear to be relatively low power:
http://www.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=215&gid=8&fid=23&category=All&showall=false

Xilinx has some PLDs, with some that are relatively low power:
http://direct.xilinx.com/bvdocs/publications/ds064.pdf

but, obviously, it depends on what total capacity you need.


some brute-force searching:
http://www.globalspec.com/ProductFinder/FindProducts?query=pld&frmtrk=topnav

TTFN

RE: 16V8 and other SPLD - power consumption

(OP)
Thanks IR. It was after looking around that I felt that I needed advice from someone that does this more routinely than I do. I'll have a look at the links. And probably feel the need for input even stronger  

RE: 16V8 and other SPLD - power consumption

Could you cut power to the devices when the clock goes away?  Obviously, you will need to be careful to make sure that none of the inputs are driven high while the power is removed, otherwise, you will power up the device through the substrate diodes and could latch up the device.

Just a thought.

RE: 16V8 and other SPLD - power consumption

(OP)
Thanks,

The problem is that the signals arrive randomly and there is no way of telling beforehand. I studied the Altera turbo feature a bit more and switching it off reduces current - but also speed. And I need 10 to 12 ns/gate or better. I do not need a complex device - only something like the 16V8 - but I need low power. The device is battery powered and uses less than 5 mA in its present form. Putting a 100 mA device in is not very attractive.

I was thinking that someone knew about low-power and fast PLDs, perhaps?

RE: 16V8 and other SPLD - power consumption

Are you looking for size reduction or re-programmability?

If the former, then it might be easier on the power to hybridize the circuitry.

TTFN

RE: 16V8 and other SPLD - power consumption

(OP)
I do not think that the small batch can justify a hybrid. I guess there will be about 200 units at most. Where do you think that a reasonable batch size is?

RE: 16V8 and other SPLD - power consumption

I've not had an opportunity to actually do one, but my understanding was that there were small hybrid specialty houses that had very low NRE and could probably handle small volumes such as 200.

TTFN

RE: 16V8 and other SPLD - power consumption

Xilinx has purchased a "zeropower" CPLD family from Philips.  They call them Coolrunner.  Actually I use the other CPLD family from xilinx, and I don't even feel the heat on my finger.  Usually you will see in the spec a curve for power consumption vs the switching frequency, and probably at a given percentage of gates running at that frequency.

One thing you have to take care about: most of these devices (xilinx and other brands as well) do not readily interface with 5-volt logic.  Some of them require series resistors, some don't, and even if some are tolerant to 5-volts, they still have a DC path to the 3.3V rail, making it harder to get 5 volts of output even with a pullup resistor.

RE: 16V8 and other SPLD - power consumption

Not sure if you're still working this, but Actel has an OTP FPGA product called the MX: http://www.actel.com/documents/MXAutoDS.pdf

They claim a max of 35 mA standby current

TTFN

RE: 16V8 and other SPLD - power consumption

The quiescent current of the CMOS is fairly low--it is due to leakage.

The running current is due to the charging & discharging
of the capacitances -- this is proportional with frequency
and depends on process  and geometry

<nbucska@pcperipherals DOT com> subj: eng-tips
read FAQ240-1032

RE: 16V8 and other SPLD - power consumption

What you say is true only for conventional static CMOS logic designs.  The Actel part in question is a one-time-programmable (OTP) part using an antifuse configuration.  

The datasheet reports ICC "Standby Current" at 35 mA.  Standby, by definition, is a static condition.

TTFN

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