tri-state bus
tri-state bus
(OP)
I am newcomer for this forum.
By the way, I am really amaze with the professional engineer answer in the forum.
I face a proble on the tri-state bus definition.
Is anybody can help me to give more details explanation on the tri-state bus application.
What is the purpose using the tri-state desing in development a chipset IC.
really appreaciate your help
By the way, I am really amaze with the professional engineer answer in the forum.
I face a proble on the tri-state bus definition.
Is anybody can help me to give more details explanation on the tri-state bus application.
What is the purpose using the tri-state desing in development a chipset IC.
really appreaciate your help





RE: tri-state bus
Basically - you can't have one device driving the line LOW or HIGH and expect another device to fight with it. Tri-state allows multiple outputs to share a bus without fighting.
RE: tri-state bus
An alternative would be to use open collector outputs. The 74LS641 is such a bus buffer. It needs a pull-up resistor on each line and it cannot be used in fast systems since the pull-up resistor cannot charge the bus lines fast enough (RC time constant too long).
RE: tri-state bus
>> Limits the amount of sourcing current, since the pulldowns must be capable of sinking that current.
>> Since the current is limited, the rising transients will be significantly slower than the falling transients
>> Since the load is always enabled, low signals will draw DC power, whereas a tri-state buffer will switch off its pulldown transistor during rising transients
TTFN
RE: tri-state bus
RE: tri-state bus
If you disable an open collector, it defaults to Logic Hi due to resistor pull ups, and there is no way (without using a set of inverters) to default it to low, however when a tri-state is disabled it is high impedence which enables you to select any load pull up or down, this load is NOT like the pullup in the sence of slowing down buss because when buss is enabled its speed is set by the driver and device input (assuming shortest connections)
For the same reason, if there is a posibility that all outs are tri stated at a time, never leave the input that they feed go floating, as any kind of faults may be expected then.
Maged A. Mohamed
http://magedm.freeyellow.com
http://www.magedsoft.com
RE: tri-state bus
TTFN
RE: tri-state bus
RE: tri-state bus
TTFN
RE: tri-state bus
RE: tri-state bus
In T.I. TTL data book the 74/54 TTL series, they have data sheets for the following ( 74L LS and S are ommitted from part number)
440 Non Inverting quad Tri Direction buss transiever.
441 Inverting quad Tri Direction buss transiever.
471 Inverting and Non Inverting buss transiever.
471,473,475 are all PROM's
289 is a 16x4 RAM
301 is a 256x1 RAM
186 and 187 is a 64x8 ROM
270 and 271 ROM
170 is 4x4 register file
156 Decoder Demultiplixer
159 4 to 16 line decoder demultiplier
All the above have chip select and or enable for expantion.
Some other manufacturers in Europe made some other seires (not 74/75) and TTL compatable and use Open collector tech.
Same tech is found in few CMOS chips and called open drain too.
Best regards
Maged A. Mohamed
http://magedm.freeyellow.com
http://www.magedsoft.com