×
INTELLIGENT WORK FORUMS
FOR ENGINEERING PROFESSIONALS

Log In

Come Join Us!

Are you an
Engineering professional?
Join Eng-Tips Forums!
  • Talk With Other Members
  • Be Notified Of Responses
    To Your Posts
  • Keyword Search
  • One-Click Access To Your
    Favorite Forums
  • Automated Signatures
    On Your Posts
  • Best Of All, It's Free!
  • Students Click Here

*Eng-Tips's functionality depends on members receiving e-mail. By joining you are opting in to receive e-mail.

Posting Guidelines

Promoting, selling, recruiting, coursework and thesis posting is forbidden.

Students Click Here

Jobs

Power dissipation in open drain CMOS

Power dissipation in open drain CMOS

Power dissipation in open drain CMOS

(OP)
I was told that an open drain CMOS requires a passive pullup resistor at the output pin. But what happens when the ouput is active low? Isn't it sinking current from the pullup and inefficiently consumes power?

RE: Power dissipation in open drain CMOS

It will only draw current when the output is active (pulling the output low), otherwise, it will draw 0 current (one side of the resistor is connected to power, while the other side is floating).  That is the whole point of an open-collector/drain output.  Therefore, many outputs can be connected to the same line, and any or all of them can assert the line (pull it low).  The most simple example of this would be a common reset line.

RE: Power dissipation in open drain CMOS

(OP)
Thanks melone for your post.
I thought that open drain outputs formed an AND function, and the inactive state is low. May be at an internal transistor level, it is an AND but at the board level, it makes sense that it is an OR (only one reset line needs to be active for the system to reset).

RE: Power dissipation in open drain CMOS

It is an AND (for positive logic) and NOR for negative logic.

TTFN

RE: Power dissipation in open drain CMOS

Open drain output are also useful for logic level translation (3 V to 5 V logic, etc). Also useful for circuits where there is more than one voltage supply which may be off, and you want to avoid the logic output from trying to power the next unpower gate through it's protection diode.

Red Flag This Post

Please let us know here why this post is inappropriate. Reasons such as off-topic, duplicates, flames, illegal, vulgar, or students posting their homework.

Red Flag Submitted

Thank you for helping keep Eng-Tips Forums free from inappropriate posts.
The Eng-Tips staff will check this out and take appropriate action.

Reply To This Thread

Posting in the Eng-Tips forums is a member-only feature.

Click Here to join Eng-Tips and talk with other members!


Resources