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White Paper: Improving Design Reliability by Avoiding Electrical Overstress

Engineers will note that when electronics fail, electrical overstress (EOS) is typically the cause.

As integrated circuit (IC) designs become more complex, they will continue to use multiple voltages, which will increase the risk of EOS.

In this 5-page white paper you will learn:
  • How EOS occurs and how it can affect an IC
  • The importance of understanding pin voltages
  • How design technology such as CALIBRE PERC can help prevent EOS

About the Author:
Matthew Hogan is a product marketing manager at Mentor Graphics with over 20 years of experience in the industry.

He has also served as a Member of the Board of Directors at the EOS/ESD Association, and as a senior applications engineer at Mentor Technologies.

Complete the form on this page to download your free white paper. Your download is sponsored by Mentor Graphics.

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